90 nanometer

Since 2002 and up to 2004, the 90 nanometer (90 nm) process has been a buzzword in the electronic, the LSI and semiconductor manufacturing, and fabrication industries. "Going beyond 90 nm" represents a breakthrough and a milestone. Related industries, such as the FPGA, network chip, DSP, flash memory chip and nanotechnology industries are also affected and are monitoring 90-nanometer trends as of 2004. Among the companies who have adopted and disclosed their 90 nanometer processes, but taking different approaches, are Intel, IBM, Texas Instruments Inc., Motorola, Fujitsu, TSMC. A majority of these companies made their disclosures in August of 2002. The 90 nanometer process refers to the average feature size. However, the minimum feature size on 90 nanometer chips can actually be quite smaller, down to around 45 nanometers.

The 90 nm point represents a milestone in the size of circuits in LSI, semiconductor manufacturing and fabrication. It is a logical effect of Moore's law. The industrial standard before this was the 0.13 micrometer (130 nm) process, and the next milestone is the 65 nm process. Smaller sizes in fabrication lead to increased circuit 'real estate' and speed, through smaller processor gates. The narrower a gate is, the faster the gate can be switched between "on" and "off". However, many modern chips are wire delay limited, meaning faster transistor speeds do not necessarily translate into faster clock speeds for the chip as a whole.

But as semiconductor technology drops to below 90 nm, the number of problems increase and there are only minimal possible improvements. Among the biggest stumbling blocks to 90 nm and finer linewidths is design for manufacturability, which includes optical proximity correction (OPC) and phase-shift technologies as well as increasing attention to yield optimization. Interconnect delays increase, leading to timing closure problems. Increased power consumption raises the heat output, and reduced feature size causes increased electromagnetic interference, more burnt tracks, more accidental interconnects and more unwanted capacitance. Because of their astonishingly small size, the walls between the wires are thin enough to allow electrons to leap between wires. This is called leakage. Some companies are attempting to solve this leakage problem by employing a technique called silicon on insulator (SOI). During the manufacturing process, a thin layer of oxide is applied to the silicon wafer, which acts as insulating material to keep electrons inside of the chip's structures.

The 90 nanometer process has an effect on circuit design methodology itself. Circuits used to be manually designed, but the large amount of 'real estate' in circuit space made available by the 90-nanometer process, plus the huge demand for a significant amount of functionality and sophistication, has forced design engineers to use Electronic Design Automation tools. Verilog, VHDL, even the C programming language and other languages are now used to convert an algorithm into a circuit.

See also

*65 nanometer
*45 nanometer
*32 nanometer

External links

*PC World Review
*IT World review
*AMD
*Fujitsu
*Intel
*August, 2002 release by Intel