Goodyear MPP
The
Goodyear Massively Parallel Processor (
MPP) was a
massively parallel supercomputer built by
Goodyear Aerospacefor the
NASA Goddard Space Flight Center. It was designed to deliver enormous computational power at lower cost thanother existing supercomputer architectures, by using thousands ofsimple processing elements, rather than one or a few highly complex
CPUs.Development of the MPP began circa
1979; it was delivered in May
1983,and was in general use from
1985 until
1991.
It was based on Goodyear's earlier
STARAN array processor, a 4x256 1-bit processing element (PE) computer.The MPP was a 128x128 2-dimensional array of 1-bit wide PEs.The PEs operated in an
SIMD (Single Instruction, Multiple Data) fashion - each processor performed the same operations simultaneously, on different dataelements, under the control of a microprogrammed control unit.
After the MPP was retired in 1991, it was donated to the
Smithsonian Institution,and is now in the collection of the
National Air and Space Museum's
Steven F. Udvar-Hazy Center. It was succeeded at Goddard by
MasPar MP-1 and
Cray T3D massively parallel computers.
The MPP was initially developed for high-speed analysis of
satellite images.In early tests, it was able to extract and separate different land-use areas on
Landsat imagery in 18 seconds, as compared with 7 hours on a DEC
VAX 11/780
.
Once the system was put into production use, NASA's Office of Space Science and Applications solicited proposals from scientists across the country to test and implement a wide range of computational algorithms on the MPP. 40 projects were accepted, to form the "MPP Working Group"; results of most of them were presented at the
First Symposium on the Frontiers of Massively Parallel Computation, in 1986.
Some examples of applications that were made of the MPP are:
|
Topographic map generated by stereo analysis |
* Signal processing of
synthetic aperture radar data
* Generating
topographic maps via
stereo analysis of satellite images
*
Mathematical modeling of
ocean circulation*
Ray traced computer graphics
*
Neural networks
* Solving large systems of
linear equations
* Simulation of
cosmic ray charged particle transport
* High resolution
Mandelbrot sets
The overall MPP hardware consisted of the Array Unit, Array Control Unit, Staging Memory, and Host Processor.
The Array Unit was the heart of the MPP, being the 128x128 array of 16,384 processing elements. Each PE was connected to its four nearest neighbors - north, south, east, and west.The array could be configured as a plane, a cylinder, a daisy-chain or as a torus.The PEs were implemented on a custom
silicon-on-sapphire LSI chip which contained eight of the PEs as a 2x4 subarray. Each of the PEs had arithmetic and logic units, 35 shift registers, and 1024 bits of
random access memory implemented with off-the-shelf memory chips.The processors worked in a
bit slice manner and could operate on variable lengths of data. The operating frequency of the array was 10 MHz. Data-bus states of all 16,384 PEs were combined in a tree of
inclusive-or logic elements whose single output was used in the Array Control Unit for operations such as finding the maximum or minimum value of an array in parallel.A register in each PE controlled masking of operations — masked operations wereonly performed on those PEs where this register bit was set.
The Array Control Unit (ACU) broadcast commands and memory addresses to all PEs in the Array Unit, and received status bits from the Array Unit.It performed bookkeeping operations such as loop control and subroutine calling.Application program code was stored in the ACU's memory; the ACU executed scalar parts of the program, and then queued up parallel instructions for the array.It also controlled the shifting of data among PEs, and between the Array Unit and the Staging Memory.
The Staging Memory was a 32 megabyte block of memory for buffering Array Unitdata. It was useful because the PEs themselves had only a total of 2 megabytesof memory (1024 bits per PE), and because it provided higher communication
bit rate than the Host Processor connection (80 megabytes/second versus 5 megabytes/second). The Staging Memory also provideddata-manipulation features such as "corner turning" (rearranging byte- orword-oriented data from the array) and multi-dimensional array access.Data was moved between the Staging Memory and the array via 128 parallel lines.
The Host Processor was a front end computer that loaded programs and datainto the MPP, and provided software development tools and networked accessto the MPP.The original Host Processor was a
PDP-11;this was soon replaced by a VAX 11/780, connected to the MPP by a DR-780 channel.
The raw computing speed for basic arithmetic operations on the MPP was as follows:
| Operation | Millions of operations per second | | Addition of arrays |
| 8-bit integers (9-bit sum) | 6553 |
| 12-bit integers (13-bit sum) | 4428 |
| 32-bit floating point numbers | 430 |
| Multiplication of arrays |
| 8-bit integers (16-bit product) | 1861 |
| 12-bit integers (24-bit product) | 910 |
| 32-bit floating point numbers | 216 |
| Multiplication of array by scalar |
| 8-bit integers (16-bit product) | 2340 |
| 12-bit integers (24-bit product) | 1260 |
| 32-bit floating point numbers | 373 |
"Appendix B. Technical Summary".
Frontiers of Massively Parallel Scientific Computation, NASA Conference Publication 2478, September 1986, pp. 289-294.
K. E. Batcher, "Design of a Massively Parallel Processor,"
IEEE Transactions on Computers, Vol. C29, September 1980, pp. 836-840.
The Massively Parallel Processor, MIT Press, August 1985, J. L. Potter, ed.
Tom Henkel. "MPP processes satellite data; Supercomputer claims world's fastest I/O rate",
Computerworld, 13 Feb 1984, p. 99.
Eric J. Lerner. "Many processors make light work",
Aerospace America, February 1986, p. 50.
