VIA C3
The
VIA C3 is an
x86 central processing unit for
personal computers produced by
VIA Technologies. Although the predecessor to the VIA C3 was called the "VIA Cyrix III," both it and the VIA C3 are based on the
CPU design technology of
Centaur Technology, makers of the
WinChip C6. VIA bought Centaur from
IDT. The C7 is a derivative of the C3 core.
The
WinChip (Centaur) core VIA purchased had a half speed FPU and no L2 cache, contributing greatly to the poor overall performance. The only positive point was that it was cheap to manufacture, with a small die size and low transistor count.
The C5X (Nehemiah) was really the breakthrough product for the Centaur derived core, although at the time VIA's marketing efforts did not fully reflect the major changes that had taken place. The numerous design shortcomings of the Winchip core, including incomplete MMX compatibility and the half speed FPU, were addressed. The number of pipeline stages was also increased from 12 to 16, to allow increases in clock speed. However, it was still based upon the aging
Socket 370, running at just 133 MHz.
VIA also appears to have realised in this period, that the small, cheap, low power characteristics of the chip, meant it was perfectly suited to high volume industrial orders in the embedded marketplace. With this in mind, in later revisions, VIA concentrated on adding features attractive to the embedded marketspace, for example in the C5XL Nehemiah VIA introduced the following:
*Twin
hardware random number generators. (These generators are erroneously called "quantum-based" in VIA's marketing literature. The
detailed analysis of the generator makes clear that the source of randomness is thermal, not quantum.)
Extended in the C5P Nehemiah:
*High performance
AES encryption in hardware
*A
Ball grid array package the size of a 1 cent coin.
According to VIA, the VIA C3 was to be superseded in 2003 by the
VIA C4 - a clone of the Intel
Pentium 4 processor. The VIA C4 naming was supposedly skipped because
C4 is a high explosive (C3 is an explosive as well, but is lesser known than C4). In September 2004 VIA announced a change of naming policy, placing all their processors in the C3 or C7 category, with an M suffix for mobile devices. The C5P (Nehemiah) is now marketed as the C3 processor, most typically sold at 1.2 GHz. At one time the VIA roadmap predicted 3 GHz by Q4 2003 based upon the C4. The nanoBGA C3 package was discontinued, reportedly because at a mere 15mm by 15mm, it was so small manufacturers had problems designing motherboards to support it.
The C7 delivers a number of improvements to the established C3 core, including a migration to a 90 nm SOI manufacturing process developed by IBM Microelectronics, at East Fishkill in New York State. The chip was designed by the old Centaur team in Austin, Texas, by a permanent staff of a mere 85 engineers.
The C7 was officially launched in May 2005, although according to market reports, full volume production was not in place at that date. In May 2006 Intel's cross licensing agreement with VIA expired and was not renewed, which was the reason for the forced termination of C3 shipments on March 31st 2006, as VIA lost rights to the 370 socket.
The C7 is sold in three main versions:
*C7 for desktops / laptops (1.5-2.0 GHz) - FCPGA Pentium-M package, 400, 533, 800 MHz FSB
*C7-M for mobiles / embedded (1.5-2.0 GHz) - NanoBGA2, 21mmx21mm, 400 MHz FSB
*C7-M Ultra Low Voltage for mobiles / embedded (1.0-1.5 GHz) - NanoBGA2, 21mmx21mm, 400 MHz FSB
New Features for the C7 include:
*2 GHz operation and a low TDP of 20 watts. For comparison, Dothan-core
Pentium M processors need 27 watts to reach 2.0 GHz.
*Level 2 cache increased from 64k to 128k, with associativity increased from 16-way set associative in C3 to 32-way set associative in C7.
*
VIA has stated the C7 bus is physically based upon the Pentium-M 479-pin packaging, but uses the proprietary VIA V4 bus for electrical signalling, instead of Intel's AGTL+ Quad Pumped Bus, avoiding legal infringement. Reviewers have found it possible to insert both Pentium-M chips and C7s into the same motherboards, this is reportedly due to VIA's
Flexi-Bus technology, which is claimed to auto-detect the CPU.
*"Twin Turbo" technology, which consists of dual
PLLs, one set at a high clock speed, and the other set at a lower speed. This allows the processor's clock frequency to be adjusted in a single processor cycle, much faster than the comparable Intel
SpeedStep technology, providing enhanced power savings.
*Support for
SSE2 and
SSE3 extended instructions.
*NX flag to reduce buffer overflows and guard against viral attacks
*Hardware support for
SHA-1 and SHA-256 hashing.
*Hardware based "
Montgomery Multiplier" supporting key sizes up to 32K for public key cryptography
The
Corefusion project combined a C3 processor and a Northbridge with integrated S3 graphics onto a single chip. While not offering leading performance, it was proposed for LCD based PCs, and other factors with extreme sensitivity to size, weight, and power consumption. John is slated to be the C7 version, due in late 2006.
| Processor | Speed
(MHz) | FSB
(MHz) | L1
cache
(KiB) | L2
cache
(KiB) | FPU
Speed | Pipeline
Stages | Max TDP
(W) | Core
(V) | (nm)>- align="center" | C5A (Samuel) | 500-667 | 100/133 | 128 | 0 | 50% | 12 | 8.5 | 1.9-2.0 | - align="center" | C5B (Samuel2) | 700-800 | 100/133 | 128 | 64 | 50% | 12 | 12 | 1.6-1.65 | - align="center" | C5C (Ezra-T) | 800-950 | 100/133 | 128 | 64 | 50% | 12 | 15 | 1.35 | - align="center" | C5M (Ezra-T) | 800-950 | 100/133 | 128 | 64 | 50% | 12 | 15 | 1.35 | - align="center" | C5N (Ezra-T) | 800-950 | 100/133 | 128 | 64 | 50% | 12 | 15 | 1.35 | - align="center" | C5X (Nehemiah) | 1-1.4 GHz | 133 | 128 | 64 | 100% | 16 | 20 | 1.4-1.45 | - align="center" | C5XL (Nehemiah) | 1-1.4 GHz | 133 | 128 | 64 | 100% | 16 | 20 | 1.4-1.45 | - align="center" | C5P (Nehemiah) | 1-1.4 GHz | 133 | 128 | 64 | 100% | 16 | 20 | 1.4-1.45 | - align="center" | C7-M (Esther C5-J) | 1.5-2.0 GHz | 400 | 128 | 128 | 100% | 16 | 20 | 0.9-1.1 | - align="center" | C7 (Esther C5-J) | 1.5-2.0 GHz | 400-800 | 128 | 128 | 100% | 16 | 20 | 0.9-1.1 | }| Processor | Secondary
Cache (k) | Die size
130 nm (mm²) | 90 nm (mm²)>- align="center" | C3 / C7 | 64/128 | 52 | - align="center" | Athlon XP | 256 | 84 | - align="center" | Athlon 64 | 512 | 144 | - align="center" | Pentium M | 2048 | N/A | - align="center" | P4 Northwood | 512 | 146 | - align="center" | P4 Prescott | 1024 | N/A | }
NOTE: Even the 180 nm Duron Morgan core (106 mm²) with a mere 64 K secondary cache, when shrunk down to a 130 nm process, would have still had a die size of 76 mm². The VIA x86 core is clearly the smallest and cheapest to produce. As can be seen in this table, four C7 cores could be manufactured for the same cost as a single core P4 on 90 nm process. | A sub-notebook utilising a VIA Nehemiah C3 processor |
While being slower than x86 CPUs being sold by AMD and Intel, both in absolute terms and on a clock for clock basis, VIA's chips are much smaller, cheaper to manufacture, and lower power. This makes them highly attractive in the embedded market space, and increasingly in the mobile sector as well.
This has also enabled VIA to continue to scale the frequencies of their chips, with each manufacturing process die shrink, while competitive products from Intel (such as the P4 Prescott) have encountered severe thermal management issues.
To this extent, the performance gap that used to exist between VIA and competing x86 chips is starting to narrow. Some of the design trade offs made by the VIA design team are worthy of study, as they run contrary to accepted wisdom.C3* Because memory performance is the limiting factor in many benchmarks, VIA processors implement large primary caches, large TLBs, and aggressive prefetching, among other enhancements. While these features are not unique to VIA, memory access optimization is one area where they have not dropped features to save die space. In fact generous primary caches (128K) have always been a distinctive hallmark of Centaur / VIA designs.
* Clock frequency is in general terms favored over increasing instructions per cycle. Complex features such as out-of-order instruction execution are deliberately not implemented, because they impact the ability to increase the clock rate, require a lot of extra die space and power, and have little impact on performance in several common application scenarios. Internally, the C7 has 16 pipeline stages.
* The pipeline is arranged to provide one-clock execution of the heavily used registerâ€"memory and memoryâ€"register forms of x86 instructions. Several frequently used instructions require fewer pipeline clocks than on other x86 processors.
* Infrequently used x86 instructions are implemented in microcode and emulated. This saves die space and reduces power consumption. The impact upon the majority of real world application scenarios is minimized.
*These design guidelines are derivative from the original RISC advocates, who stated a smaller set of instructions, better optimized, would deliver faster overall CPU performance.C7* C7 Esther as an evolutionary step after C3 Nehemiah, in which VIA / Centaur followed their traditional approach of balancing performance against a constrained transistor / power budget.
*The cornerstone of the C3 series chips design philosophy has been that even a relatively simple in-order scalar core can offer reasonable performance against a complex superscalar out-of-order core if supported by an efficient "front-end", i.e. prefetch, cache and branch prediction mechanisms.
*As can be evidenced from this article, in the case of C7 the design team have focused on further streamlining the "front-end" of the chip, i.e. cache size, associativity & throughput as well as prefetch system. At the same time no significant changes to the execution core ("back-end") of the chip seem to have been made.
*The C7 successfully further closes the gap in performance with AMD / Intel chips, since clock speed is not thermally constrainedVIA's embedded platform products have reportedly (2005) been adopted in Nissan's car series, the Lafesta, Murano, and Presage. These and other high volume industrial applications are starting to generate big profits for VIA as the small form factor and low power advantages close embedded deals.C7*An inside look at the VIA C7-M, by Van Smith
*Via chips missing in action
*Review of the EPIA EN15000 with VIA C7 Processor
*Review of the VIA C7-M powered TongFang notebook
*VIA C7 Processor
*VIA C7-M Processor
*C7 @ 2 GHz - comparable performance to a 1.3 PIII, in French
*Detailed Platform Analysis in RightMark Memory Analyzer. Part 12: VIA C7/C7-M Processors, in Russian
*Detailed Platform Analysis in RightMark Memory Analyzer. Part 12: VIA C7/C7-M Processors, translated in English
*One of the first C7 benchmarks, in Chinese
*VIA EPIA EN12000E: Today's most efficient CPU & mainboardC3*VIA-C3-Nehemiah review
*VIA C3 Gold CPU - 1 GHz
*VIA's Small & Quiet Eden Platform
*GHz_processor_review/ VIA C3 1 GHz Processor Review
*BlueSmoke - Review : VIA C3 ProcessorGeneral*http://www.cpushack.net/VIA.html
*http://www.digit-life.com/articles/viacyrix3/
*http://www.sandpile.org/impl/c5xl.htm
|
|---|
|
|---|
